A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories
Y. Miyawaki, T. Nakayama, S. Kobayashi, N. Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tatsuhiko Yoshihara · IEEE Journal of Solid-State Circuits · 1992
To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.>