A serial input VLSI systolic architecture for a clustering analyser
MAO-FU LAI CHAUR-HER HSIEH · International Journal of Electronics · 1998
A serial input VLSI architecture is presented for squared error clustering analysis based on a systolic array. The proposed systolic architecture uses a simple, regular and modular design that can considerably reduce the circuit complexity. The architecture requires only local communication between adjacent processing elements, and is adaptable to accommodate a variation in the number of input patterns. In addition, the proposed architecture allows data to be input in featureserial format to save enormous pin counts, which is essential for VLSI implementation. Using this novel architecture, the VLSI implementation for high throughput clustering analysis can be realized cost-effectively.