Automatic program generator for simulation-based processor verification
H. Iwashita, S. Kowatari, Tsuneo Nakata, Fumiyasu Hirose · 2002
This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods.>