10-ns row cycle DRAM using temporal data storage buffer architecture
S. Wakayama, Katsunori Gotoh, M. Saito, H. Araki, Tsz-Shing Cheung, J. Ogawa, Hirotaka Tamura · 2002
We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.