System-level verification on high-level synthesis of dataflow graph
Tsung-Hsi Chiang, Lan-Rong Dung · 2006
This paper presents a system-level verification algorithm using the Petri net theory to detect design errors for high-level synthesis of dataflow graphs. Typically, given a dataflow graph and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto silicon. Many tools exist for RTL design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri net theory to verify the correctness of the synthesis result. Herein, we propose three approaches to realize the Petri net based formal verification algorithm and identify the best one that outperforms the others in terms of processing speed and resource usage.