Impact of partial reset on fault independent testing and BIST
Huy Thong Nguyen, Ranjan Roy, Abhijit Chatterjee · 2002
Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/reset) is performed periodically while the test input vectors to the sequential circuit are applied. An average improvement of 15% in fault-coverage has been obtained for circuits resistant to random pattern testing.