A cost-efficient and fully-pipelinable architecture for DCT/IDCT
Shen‐Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng · IEEE Transactions on Consumer Electronics · 1999
A novel low-cost and low-power linear array for computation of discrete cosine transform (DCT) and its inverse is derived from the heterogeneous dependence graphs representing the factorized coefficient matrices. Due to the novel algorithm and the corresponding efficient architectural design, the new DCT/IDCT processor is easily pipelined and the power consumption can be reduced significantly by turning off the operation of arithmetic units whenever possible.