Analysis, Design and Performance of a Frequency-Synthesizer Loop Using Sample-Hold-Delay-Sample-Hold Phase-Detector
Swapan Sen, K.S. Patel · IETE Journal of Research · 1979
A new method of design for a synthesizer-loop using sample-hold-delay-sample-hold phase-detector is given. It makes the design of such loops straightforward and easy. The method is utilised in the design of a typical synthesizerloop having frequency range of 8 to 9 MHz (in steps of 250 Hz), settling time of 40 ms and greater than 110 dB suppression of unwanted spurious sidebands at its output.