An implementation of a gigabit ethernet AES encryption engine for application processing in SDR
Daniel Denning, James M. Irvine, Neil Harold, Paul A. Dunn, Malachy Devlin · 2005
We present a gigabit Ethernet AES (Advanced Encryption Standard) encryption engine. One of the main push factors in software-defined radio (SDR) is the use of programmable devices such as field programmable gate arrays (FPGAs) or digital signal processors (DSPs). Including such devices in SDR base station systems allows for reconfiguration and upgrade of the communication system and the application processing. Due to the increased concerns regarding secure information, we have implemented an AES encryption engine for data processing in an SDR system using one of the latest FPGAs available. The engine is capable of simultaneously processing 2 input and 2 output data streams of 1 gigabit each. As the system has been developed on an industrial scalable architecture, a further 3 FPGA daughter cards can be added to the board for further application processing, and each board could be one of many.