FPGA Implementation of Block Parallel DF‐MPIC Detectors for DS‐CDMA Systems in Frequency‐Nonselective Channels
Adel Omar Dahmane, Lotfi Mejri · Journal of Electrical and Computer Engineering · 2008
Multistage parallel interference cancellation‐ (MPIC‐) based detectors allow to mitigate multiple‐access interference in direct‐sequence code‐division multiple‐access (DS‐CDMA) systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF) is employed. Although MPIC and DF‐MPIC have the same arithmetic complexity, DF‐MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF‐MPIC (BP‐DF‐MPIC) is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit‐error rate of 10−3, BP‐DF‐MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF‐MPIC.