Integrating formal methods tools to support system design
Shiu‐Kai Chin, J. Faust, Joseph V. Giordano · 2002
System engineering requires design and verification at several levels of abstraction-from top-level process descriptions down to gate-level hardware designs. A variety of tools such as specification languages, simulators, model checkers, theorem-provers, and other computer-aided design tools are used for designing and verifying systems. These tools must be integrated to support a continuous design flow. We report on the theoretical and practical aspects of integration and discuss our experience with specific tools.