Design and implementation of a 100 MHz reorder buffer
Steven Wallace, Nadir Dagli, Nader Bagherzadeh · 2002
A reorder buffer is an important part of a superscalar microprocessor architecture. It allows out-of-order issue and completion of instructions, which contribute to overall performance enhancement. A custom layout of a 32-entry reorder buffer was implemented using a 1.0 /spl mu/m (drawn) triple-metal CMOS technology. It measures 2 mm by 2.85 mm. The design was verified using several benchmark programs.