A Real-time Implementation Of Key VSELP Routines on a 16-bit DSP Chip
Myung Hoon Sunwoo, S. Park, K. Terry · 2005
This paper dkcusses a teal-time implementation of the Vector Sum-Excited LhsearPredictive WSELP) stx?ech coder which hm tin chosen as the digital cellular st&dard ~ North America and Japan. A real-time implementation of the VSELP algorithm cars be reaMzed using a Motorola digital signat processor, the DSP56 156. The principles of the VSELP algorithm, the real-time implementation of the algorithm on the DSP56 156, aud finite word-length effects are considered in the following discussion.