Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors
H.-J. Wunderlich, Maik Herzog, Joan Figueras, Juan Antonio Carrasco, A. Millán · European Design and Test Conference · 1995
On-Chip I/sub DDQ/ testing by the incorporation of Built-In Current (BIC) sensors has some advantages over off-chip techniques. However, the integration of sensors poses analog design problems which are hard to solve for a digital designer. The automatic incorporation of the sensors using parameterized BIC cells could be a promising alternative. The work reported here identifies partitioning criteria to guide the synthesis of I/sub DDQ/-testable circuits. The circuit must be partitioned, such that the defective I/sub DDQ/ is observable, and the power supply voltage perturbation is within specified limits. In addition to these constraints, cost criteria are considered: circuit extra delay, area overhead of the BIC sensors, connectivity costs of the test circuitry, and the test application time. The parameters are estimated based on logical as well as electrical level information of the target cell library to be used in the technology mapping phase of the synthesis process. The resulting cost function is optimized by an evolution-based algorithm. When run over large benchmark circuits our method gives significantly superior results to those obtained using simpler and less comprehensive partitioning methods. >