A real-time systolic array for distance transformation
Dyi-Long Yang, Chin‐Hsing Chen · 2002
This paper proposes a systolic array for weighted DT. For a 512/spl times/512 image, the design presented in this paper needs only 0.6 ms to complete the DT, which outperforms current existing designs. The architecture is modular and regular, and well suited to VLSI implementation. Both the time and processor complexity of the architecture are linear to the image size. For a column array processor to perform at the above speed, its hardware cost is about 52 times as expensive as the authors' design.