A highly-flexible FIR processor with scaleable dynamic data ranges
Wei-Lung Liu, O.T.-C. Chen, Hsun-Chang Hsieh, Jeng-Yih Wang · 1998
A highly-flexible finite impulse response (FIR) architecture with scaleable dynamic ranges of input data and filter coefficients is proposed based on the radix-4 Booth algorithm. In order to achieve scaleability, the configurable-connection function between input data latches and filter taps has been explored. The precision of filter coefficients is adjustable by using a path-control function. Especially, the proposed architecture only employs data-path controls to realize the scaleable issue without changing word lengths and components of input latches and filter taps. Based on our architecture, a typical FIR processor with 64-tap 8-bit and 32-tap 16-bit operations was implemented by using the COMPASS 5V cell library in the TSMC 0.6 /spl mu/m CMOS technology. Its die size is around 8.0/spl times/8.0 mm/sup 2/ with a power consumption of 2.9 W at a system clock of 100 MHz.