A High-Speed and Area Efficient Hardware Implementation of AES-128 Encryption Standard
Andreas Brokalakis, Harris E. Michail, Athanasios P. Kakarountas, Eleni Fotopoulou · 2014
Abstract:- The Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.