A yield and speed enhancement scheme under within-die variations on 90nm LUT array
Kazuya Katsuki, Motoko Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera · 2006
In this paper, we propose a yield and speed enhancement scheme using a reconfigurable device. An LUT array LSI is fabricated on a 90nm process to measure process variations of LUTs. D2D and WID variations are clearly observed. Reconfiguration using the measurement process variations boosts yield and also increases the average operating speed by 4.1%. In addition, it is proved that expansion of WID variations make the proposed method more effective