High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000
Kuizhi Mei, Nanning Zheng, Huub van de Wetering · Electronics Letters · 2006
A highly pipelined line-based one-level 2D discrete wavelet transform (DWT) VLSI design is proposed using two line-FIFOs in 5/3 wavelet type and performing with input speed up to 2 samples/cycle. Furthermore, a recursive multi-level wavelet decomposition architecture using a dual buffer scheme is proposed to reduce the memory for wavelet coefficients to 1/4 Tile size. The two proposals allow for a 2D DWT architecture for JPEG2000 that is both high-speed and memory-efficient.