Dynamic vectorization in the E2 dynamic multicore architecture
Andrew R. Putnam, A. Gordon Smith, Doug Burger · ACM SIGARCH Computer Architecture News · 2010
Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efficient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2's support for dynamic reconfigurability and show how the EDGE ISA facilities outof- order vector execution.