Autonomous buffer controller design for concurrent execution in block level pipelined dataflow
Magesh Sadasivam, Sangjin Hong · IEEE Computer Society Annual Symposium on VLSI · 2004
This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.