R-NUCA: Data Placement in Distributed Shared Caches
Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki · 2009
Increases in on-chip communication delay and the large working sets of commercial and scientific workloads complicate the design of the on-chip last-level cache for multicore processors. The large working sets favor a shared cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests. At the same time, the growing on-chip communication delay favors core-private caches that replicate data to minimize delays on global wires. Recent hybrid proposals offer lower average latency than conventional designs. However, they either address the placement requirements of only a subset of the data accessed by the application, require complicated lookup and coherence mechanisms that increase latency, or fail to scale to high core counts. In this work, we observe that the cache access patterns of a range of server and scientific workloads can be classified into distinct categories, where each class is amenable to different data placement policies. Based on this observation, we propose Reactive NUCA (R-NUCA), a distributed shared cache design which reacts to the class of each cache access and places blocks at the appropriate location in the cache. Our design cooperates with the operating system to support intelligent placement, migration, and replication without the overhead of an explicit coherence mechanism for the on-chip last-level cache. We evaluate R-NUCA on a range of server, scientific and multi-programmed workloads and find that its performance matches the best alternative design, providing a speedup of 17 % on average against the competing alternative, and up to 26 % at best.