Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates
Naman Sharma, Upanshu Saraswat, Rakesh Sachdeva · 2014
Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible binary multiplier design. It also juxtaposes the three proposed architectures to compare their properties and hence propose the most optimized form of the aforementioned multipliers.