Design, Synthesis, and Test of Networks on Chips
Partha Pratim Pande, Cristian Grecu, A. Ivanov, R. Saleh, Giovanni De Micheli · IEEE Design & Test of Computers · 2005
For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.