Simple parallel weighted order statistic filter implementations
M.J. Avedillo, José María Quintana, Esther Rodriguez–Villegas · 2003
This paper describes a simple parallel architecture for the implementation of Weighted Order Statistic Filters (WOS), an. important class of digital nonlinear filters. The new architecture combines the design easiness of stack architectures with the area efficiency of those based in ordering matrices. It decomposes the M-valued signals into a reduced number of binary signals which are filtered by identical Boolean logic circuits. Both area-efficient and fast implementations are obtained straight-forward from filter specifications. The design of a complex WOS filter is described. Results show a sample frequency over 60 MHz in a 0.35 /spl mu/m CMOS technology.