A comprehensive instruction fetch mechanism for a processor supporting speculative execution
Tse-Yu Yeh, Yale N. Patt · ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter · 1992
A superscalar processor supporting speculative execution requires an instruction fetch mechanism that can provide instruction fetch addresses as nearly correct as possible and as soon as possible in order to reduce the likelihood of throwing away speculative work. In this paper we propose a comprehensive instruction fetch mechanism to satisfy that need. Implementation issues are identified, possible solutions and designs for resolving those issues are simulated, and the results of these simulations are presented. A metric for measuring the average penalty of executing a branch instruction is introduced and used to evaluate the performance of our instruction fetch mechanism. We achieve an average performance of 4.19 IPC on the original SPEC benchmarks in a machine which can execute five instructions ideally by using the proposed mechanism. 1 Introduction The importance of instruction fetch becomes vital as deeply-pipelined superscalar machines become prevalent due to the corresponding...