Scalable FPGA design and performance analysis of PHASH hashing function
Przemyslaw Zalewski, Marcin Łukowiak, Stanisław Radziszowski · 2009
Abstract — This paper presents an FPGA design and performance analysis of a recently proposed parallelizable hash function – PHASH. The main feature of PHASH is that it is able to process multiple data blocks at once making it suitable for achieving ultra high-performance. It utilizes the W cipher, as described in the Whirlpool hashing function at its core. A Virtex-4 FX60 FPGA was used in order to verify functionality of the implementation of the algorithm in hardware. To achieve high performance, state-of-the-art Virtex-5 LX330 FPGA was used as target platform. PHASH achieved a throughput over 15 Gbps using a single W cipher instance and 182 Gbps for 16 instances. For fair comparison of the performance of PHASH with widely accepted SHA-512 and Whirlpool hashing functions we have also developed their high performance implementations targeting the same FPGA platforms. SHA-512 implementation attained a throughput of 1828 Mbps, and Whirlpool attains 7687 Mbps. Index Terms — scalable FPGA design; hash function; performance analysis. I.