Design and Implementation of High Speed RNS Input-Output Converters
Kavita Mehta, V.R. Sudershan · 2005
Residue Number System (RNS) based Digital Signal Processing (DSP) Systems that use 2’s complement representation for input and output require conversion from binary-twresidue and residue-t*bhxy at input and output respectively. In many high speed systems, speed and efficiency of these conversions become critical. In this paper, we present two designs in 0.8 micron CMOS technology - a Systolic Array based on Universal I/O RNS Converter [Meeh 901 and another using Read Only Memory (ROM) array. The designs developed as generatm/compilers, SPICE simulation model and the performance are described in detail. Initial simulation results predict performance of over 50 MHz clock speed.