A 300-MHz 16-b BiCMOS video signal processor
Toshiaki Inoue, J. Goto, M. Yamashina, Kazumasa Suzuki, Masahiro Nomura, Yoshiyuki Koseki, Tsukasa Kimura, T. Atsumo, Masato Motomura, Benjamin S. Shih, T. Horinchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada, M. Takada · IEEE Journal of Solid-State Circuits · 1993
A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area.>