Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator
Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu · 2007
Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.