Static property checking using ATPG vs. BDD techniques
Chung-Yang Ric Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Tim Cheng · 2002
Static property checking verifies pre-defined functional design rules such as "bus contention", "racing condition"; and "don't-care case". A static property checker typically uses formal verification techniques to prove the property under verification. If the property is proven false, a counter-example is generated for debugging the design. Among the different static property checking approaches, ATPG-based and BDD-based are the most powerful and successful ones. We implement both approaches with several optimization techniques on the same framework to compare their performance. The experimental results on industrial designs show that these two approaches have different strength and weakness in proving the static properties. Furthermore, the results indicate that they often complement each other and therefore a hybrid approach may result in better performance. We propose a static property checker based on combined ATPG and BDD techniques. The experimental results show that this combined approach can prove all the static properties in the test cases while still maintaining comparable performance.