Facilitating superscalar processing via a combined static/dynamic register renaming scheme
Eric Sprangle, Yale N. Patt · 1994
A superscalar implementation of a conventional in-struction set architecture (ISA) requires N(N- 1) com-parators to determine dependencies between the N in-structions issuing concurrently [2] and 2N register file read ports to handle the 2 operands that each instruc-tion can potentially source. On the other hand, if the compiler is allowed to specify part of the renaming tag, we show that we can eliminate the comparators needed to detect data dependencies between instructions issu-ing concurrently, and we can reduce the number of read ports from 16 to about 7 without losing performance. Finally, we show that this approach more efficiently im-plements predicated execution than can be done with a convent ional ISA on a machine that renames registers.