Time-area efficient multiplier-free recursive filter architectures for FPGA implementation
M. Shajaan, John Aasted Sørensen · 2002
Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (17 bits internal data representation). It is demonstrated that the time-area efficiency and performance of the architectures are considerably above any known approach.