A development system for an SRAM-based user-reprogrammable gate array
Yudai Shibata, H. Funatsu, Y. Ishida, J. Yoshida · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.>