Parallel architectures for computing the Hough transform and CT image reconstruction
Lifei Lin, V.K. Jain · 2002
This paper discusses high-speed array implementations of two image processing algorithms, namely the 'Hough transform for detection of line segments', and 'backprojection in CT image reconstruction'. A multi-chip-module (MCM) construction is proposed consisting of three types of chips, a high speed multi-function nonlinear chip, a flexible multiply-accumulate chip, and an image kernel chip. Called V-array, it can be configured to have eight Hough modules, so as to produce the Hough transform of a 1024/spl times/1024 image in an estimated 13 ms in 2.0 micron CMOS technology (6.6 ms in 1.0 micron CMOS technology). Similarly, a V-array MCM can accommodate eight CT modules, which can produce the backprojected image in 209 ms in 2.0 micron CMOS technology (105 ms in 1.0 micron CMOS technology). To gain a significant speed advantage, we have developed an advanced multi-function cell for performing any one of four nonlinear operations: square-root, reciprocal, sine/cosine, and arctangent-all realized in a single chip, accessible on a selectable basis. A 16 bit four-function "one cycle" VLSI chip, fabricated in 2.0 micron CMOS technology, is presently available which outputs a new result every clock cycle. Using this nonlinear cell and two other cells, an application level Hough transform module and a CT module are presented.>