A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition
Haridimos T. Vergos, Constantinos E. Efstathiou · IEEE Transactions on Circuits & Systems II Express Briefs · 2008
In this paper, it is shown that every architecture proposed for modulo 2n+1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo 2n+1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.