A design methodology for high-performance and low-leakage fixed-point transpose FIR filters
Dimitris Bekiaris, Sotiris Xydis, George Economakos, Kiamal Pekmestzi · 2009
This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-VthCMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-VthMultiplication-Addition units by their high-Vthcounterparts, taking into account the timing slack of each unit and the word-level binary representation of the units' coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69-25.85% for several clock period constraints, compared to the low-VthFIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.