A 1062Mpixels/s 8192×4320p High Efficiency Video Coding (H.265) encoder chip
Sung-Fang Tsai, Chung‐Te Li, Hsuan-Hung Chen, Pei-Kuei Tsung, Kuan‐Yu Chen, Liang‐Gee Chen · 2013
A single-chip HEVC (H.265) 8192×4320p encoder is implemented on a 25mm2 die with 28nm process. It dissipates 708mW at 312MHz for 8192×4320p encoding. Frame-level pipelining reduces 8.90 GB/s external memory bandwidth and improve CABAC rate by 50%. A 7.14MB three-level memory hierarchy is designed to support internal 43.38 GB/s bandwidth and 13-port accesses, and reduces external reference frame bandwidth down to 2.97 GB/s. High complexity mode decision is supported with CFBAC rate estimator.