New methods of improving parallel fault simulation in synchronous sequential circuits
Hyung Ki Lee, Dong Sam Ha · International Conference on Computer Aided Design · 1993
A highly successful parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. We propose several new techniques which further reduce the fault simulation time of HOPE. The new techniques are: functional fault injection, static fault ordering by fanout free regions and dynamic fault ordering of potentially detected faults. The three methods are incorporated into HOPE and called HOPE1.1. HOPE1.1 shows significant improvement in performance for all the benchmark circuits experimented as compared to HOPE. Experimental results show that HOPE1.1 is especially effective for large circuits. For s35932 which is the largest circuit experimented with, the number of events is reduced by 24%, and the CPU time by 53% compared to HOPE.