Memory, control and communications synthesis for scheduled algorithms
Douglas M. Grant, Peter B. Denyer · 1990
This paper explores a method of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimised. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimisation are illustrated with an example.