Platform Independent Test Access Port Architecture
Arie Margulis, D. Akselrod, T. Wood, S. Metsis · 2008
In this work, we present and analyze a generic test access port (TAP) architecture capable of being re-used without any modifications in various system-on-chip (SoC) ICs as well as a "modular Jtag" multi-TAP architecture that allows embedded IPs to control their boundary-scan segments and be IEEE 1149.1 compliant.