Harvest rate of reconfigurable pipelines
Weiping Shi, Ming-Feng Chang, W.K. Fuchs · IEEE Transactions on Computers · 1996
For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. The authors give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: there are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, they prove when n=/spl theta/(m), the harvest rate is between 34% and 72%.