An efficient 2-D convolver chip for real-time image processing
Se Young Eun, Myung Hoon Sunwoo · 2002
This paper proposes a new real-time 2-D convolver filter chip without using any parallel multiplier. The proposed chip uses only one special shift-and-accumulation lock instead of nine multipliers. Hence the chip can reduce the chip size by more than 70% of commercial 2-D convolver chips. Moreover, the proposed chip does not require row buffers to control input data sequence employed in commercial chips. We implemented the filter chip using the 0.8 /spl mu/m SOG cell library (KG60K). The filter chip consists of only 3893 gates, operates at 125 MHz and can meet the real-time image processing requirement, i.e., the standard of CCIR601.