Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices
Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, M. Kido, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Yuzo Nagata, Li Zhang, Yoshihisa Iwata, R. Kirisawa, Hideaki Aochi, Akihiro Nitayama · Symposium on VLSI Technology · 2006
We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 mum2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the multi-level-cell (MLC) operation by 60 nm P-BiCS flash technology.