A self clocked FPGA for general purpose logic emulation
Dana L. How · 2002
This paper describes the architecture of an entirely self-clocked FPGA. Such an FPGA would avoid clock distribution problems, facilitate circuit composition and increase the amount of hardware concurrency, as well as reliably operate at its maximum speed without timing analysis. These unique advantages would be of great use in many functional simulation and logic emulation applications targeting larger designs requiring many FPGAs.