Hardware technology for the Hitachi MP5800 series (HDS Skyline Series)
F. Kobayashi, Yoshio Watanabe, Koki Kasai, K. Koide, K. Nakanishi, Ryota Sato · IEEE Transactions on Advanced Packaging · 2000
The Hitachi MP5800 series (HDS Skyline Series/sup TM/) has been developed as the top-of-the-line member of the M Parallel Series general computer family. Its highlights include the highest processor performance, dramatically reduced installation requirements (footprint and power consumption), and enhanced reliability and availability. To achieve these goals, innovative technologies have been developed: semiconductor technology called Advanced CMOS-ECL (ACE), which combines high speed emitter coupled logic (ECL) and high density complementary metal oxide semiconductor (CMOS) circuits, one-module processor, which employs a glass ceramic substrate, a high density packaging scheme whereby up to four instruction processors (IPs) are mounted on a single printed wiring board, a cooling technology for large scale integration (LSI) chips with a power consumption as high as 140 W/chip, and a compact high-efficiency power supply system.