Designing self-testable cellular arrays
Cheng‐Wen Wu, S.-K. Lu · 2002
Design-for-testability techniques and built-in self-test structures are presented for cellular arrays based on the M-testability condition, which results in the minimal number of tests. This technique applies to arrays with arbitrary dimensions and various connections. A systolic array multiplier is given as an example, showing an overhead of only 4% for making it M-testable. This method compares favorably with that based on pI-testability. It reduces drastically the testing costs for circuits realized as cellular arrays.>