Framework for Fault Analysis and Test Generation in DRAMs
Zaid Al-Ars, Said Hamdioui, G. Mueller, A.J. van de Goor · Design, Automation, and Test in Europe · 2005
With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory test problem. This paper describes a framework of algorithms and tools developed jointly by the Delft University of Technology and Infineon Technologies to systematically generate DRAM tests using Spice simulation. The proposed Spice-based test approach enjoys the advantage of being relatively inexpensive, yet highly accurate in describing the desired memory faulty behavior.