Yield loss forecasting in the early phases of the VLSI design process
H.T. Heineken, Jitendra B. Khare, Wojciech P. Maly · 2002
This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.