An ASIC implementation of phase correlation based on run-time reconfiguration technique
Naoto Miyamoto, Katsuhiko Hanzawa, Tadahiro Ohmi · 2009
In this paper, we present an application-specific LSI that is designed using a run-time reconfiguration technique. The implemented algorithm is phase correlation. The calculation of phase correlation includes Fast Fourier Transform (FFT) followed by Inverse Fast Fourier Transform (IFFT). We have developed a dual-decimation butterfly module that can be self-reconfigured, at run-time, to be either decimation-in-time (DIT) or decimation-in-frequency (DIF). By sharing the common parts between the DIT and DIF butterfly modules, the dual-decimation butterfly module can reduce the logic size to about half. DIT-mode is used for FFT and DIF-mode is used for IFFT. No data reordering, such as natural-to-reverse or reverse-to-natural conversion, between FFT and IFFT is necessary. As a consequence, the amount of intermediate frame buffers and the number of memory accesses are significantly reduced.